1. Field of the Invention
The present invention relates to a manufacturing technique for a MOS transistor semiconductor device, and more particularly, to a MOS transistor having a double LDD structure and a manufacturing method thereof.
2. Discussion of the Related Art
In the early days of semiconductor integrated circuits, a silicon die having a size of 1-2 mm was generally required for each transistor. Currently however, millions of unit elements can be integrated on a silicon die having a size of 20 mm×20 mm. The size of a unit transistor should be minimized in order to manufacture such integrated circuit, and to this end, various processing techniques are being developed.
As the unit transistor of an integrated circuit has been scaled down, a substrate having a source-drain diffusion area that is deeply diffused and a highly thin junction having a large curvature is utilized. In a drain-substrate junction, in which impurities have a sharp concentration gradient, impact ionization may occur due to a hot carrier. To address this issue, a lightly doped drain (LDD) structure has been utilized. The LDD is structured such that a boundary of a polysilicon gate is first determined, and an LDD extension line determining a channel extension is subsequently formed using an N-type impurity implantation.
Meanwhile, after a gate electrode and a source-drain diffusion area of a transistor are formed, a contact with metal wiring is formed so that the gate electrode and the source-drain diffusion area can be electrically connected. At this time, a thin polysilicon gate and a shallow source-drain diffusion area are formed due to the scaling down of a transistor, such that both of resistances thereof cannot be reduced to be less than 10-20 ohms/square. For this reason, the efficiency of an interconnection material is significantly decreased.
To address this issue and improve interconnection, a method of forming a silicide having a low resistivity on a silicon of a gate or a source-drain area has been utilized. Particularly, a process for forming a silicide on the gate and the source-drain area of a transistor concurrently is called a salicide process. Through the salicide process, a parasitic transistor can be removed, which may occur when the source-drain and the gate overlap, and since the contact space of a metal and the source-drain increases, the contact resistance and inner resistance of the source-drain can be reduced.
FIGS. 1A-E illustrate a conventional method of forming an LDD and a salicide of a semiconductor device.
First, a gate oxide 20 and a polysilicon 30 are sequentially formed on a substrate 10 in an active area for forming a transistor, and subsequently, a patterning is performed only in an area for forming a gate electrode thereon by photolithography and etching processes, as shown in FIG. 1A.
Next, impurity ions having an opposite conductive type with respect to the substrate 10 are implanted with a low concentration and a low energy using the poly silicon gate 30 as a mask, which is formed as shown in FIG. 1A, and is thermally annealed to form an LDD area 22a as shown in see FIG. 1B.
After the LDD area 22a is formed, an oxide layer is formed on the whole surface of the substrate 10 using a low pressure chemical vapor deposition (LPCVD), and the oxide layer is then etched and removed except for an oxide layer on lateral walls of the gate 30. The oxide layer remaining on the lateral walls of the gate 30 is a spacer 32 that prevents a short between a gate and a source-drain diffusion area that may occur in an after-mentioned salicide process. The spacer 32 is formed as shown in FIG. 1C.
Next, as shown in FIG. 1D, impurity ions are implanted and thermally annealed using the poly silicon gate 30 and the spacer 3 as a mask to form a source-drain diffusion area 22b with a high concentration. Next, a metal such as cobalt (Co) or titanium (Ti), which forms a salicide in reaction with silicon or polysilicon, is deposited on the whole surface of the substrate 10. Next, a salicide layer is formed on a polysilicon gate and on a silicon substrate of the source-drain diffusion area in an annealing process, and subsequently, any metal that has not been reacted is removed by selective etching. A self aligned silicide formed in this way is referred to a salicide. FIG. 1E shows salicide layers 24a and 24b which are respectively formed on the polysilicon gate 30 and the source-drain diffusion area.
However, the aforementioned manufacturing method of a semiconductor device has at least following problems.
First, as a circuit is highly integrated, unit transistor elements become closer to one another. At this time, as gate electrodes of transistors are disposed adjacent to one another, the distance between the gates becomes very small. Thus, an exposure area of a source-drain diffusion area between the gates having the oxide spacer 32 becomes small. As shown in FIG. 2, a salicide forming area becomes very narrow in the source-drain diffusion area. As a result, free space for forming a contact becomes narrow, and the salicide does not form well and surface resistance increases.
Second, in order to prevent a lateral diffusion of impurities when the LDD is formed, a junction has to be shallowly formed. However, due to the scaled down transistor element, if a gate width is narrowly designed, a short channel effect becomes serious. Namely, as the width of the gate decreases, the depth of the LDD area and the concentration of the impurities become difficult to control, and as such, the lateral diffusion of the impurities towards the gate is difficult to control. Therefore, the gate and the drain overlap in an area, and if the overlapping area increases, resistance and parasitic capacitance increase.